ok. my apologizes.

there really are tons of things to consider with that question. RISC has historically allowed for faster clocking and fewer cycles per instruction, so thats a win. RISC also requires more instructions per useful operation and also blows up the binary size, so… :-(

all things being equal (hahaha) RISC has more headroom and legroom for future improvements that dont complecate the silicon to extreme degrees. the vast majority of CISC designs are now pretty RISC-like at their cores, but the software interface remains CISC and, I think, complicates and limits variety and advancement.

imho, a properly spec’d RISC processor and a carefully designed compiler, cycle for cycle, macro for macro and watt for watt outperforms a CISC design (even with a RISC-like core). major computing holy wars are been waged over this for decades.

all I currently have access to are older studies that show mixed general purpose results on RISC vs CISC (performance, not power efficiency), but if I had to make a choice about what my future ideal processor would be, it would be RISC core and RISC instruction set architecture simply due to less complexity, more efficient use of wafer space and lower power requirements. then we start talking about massively parallel RISC in tiny spaces and, for many (but not all) workloads, thats a big win.

this is so deliciously and disappointingly true. :-/

CPI per CPI… RISC, but thats a trap of a question and you know it ;-)

tons of variables in that question, but there should be more headroom in RISC designs and thats why, internally, most things are RISC-y.

meh (not dismissive - just cute), ecosystem mootness is overrated. at the heart of every CISC beats a RISC. strip away the mask and lets poke the nuclear core.

great reply. I am not saying RISC is the panecea, what I am saying is that there are more options for workload optimization further up the stack and rebalancing of the intelligence from the silicon to the software is an advantage.

some time ago most CISC core design become more RISC-y and, to indulge in some ISA snobbery, I just want to slash and burn the CISC presentation to the software layer. memory is cheap, bus bandwidth is insane - simplification on the ISA just seems like a hardware complexity win all around and I am willing to pay for that in compiler complexity that incorporates changes more easily than hardware or CISC microcode.

RISC-V’s challenge is can they standardise the software ecosystem enough[…]

agreed. this is why I say my wait may be coming to an end.

personally, I think RISC is the more flexible design in almost every usecase. cycle for cycle, RISC hits the right buttons for me across the widest number of situations once we get above the “magic hardware” layer. willing to flog the CISC vs RiSC horse convo if you have recent information, and thanks for the response.

between the 30k’ overview of Reduced instruction set computer (RISC) architecture and the lower level RISC-V Architecture: A Comprehensive Guide to the Open-Source ISA, you should get a pretty decent feel for it.

the level of optimization you get via hardware and software tooling is honestly pretty spectacular. I have been waiting for RISC to come out of hiding for years and it seems to be happening.

“reduced” is the super power. I would much rather put the smarts into the assembler/compiler/interpreter than the silicon. have been followed RISC since the 80’s and discovered that I am really a RISC guy living in CISC world. open arch is the world dominating cherry-on-top.

was at my local post office on that day. postal worker was watching it on her lunch break. ended up in a really good convo about the current admin, probable doge action against USPS and civil resistance in general.

it was a social connection between two people that reinforced personal conviction. to me (and perhaps her as well), that was priceless.

and, honestly, RISC-V is the right place to spend it. RISC has super powers.